1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to the structure of a contact hole that connects a diffused layer and a metallic wiring in a semiconductor device having at least a groove type element isolation region.
2. Description of the Prior Art
In semiconductor devices that include MOS transistors, fine patterning is in progress for the purpose of enhancing the integration and operating speed of the semiconductor devices. For example, in a MOS transistor, fine patterning is being realized by the reduction of the gate length of the gate electrode, the reduction of the area of the diffused layer forming the source and drain region, the reduction of the width of the element isolation region between the MOS transistors, and the like. A reduction in the gate length lowers the on-resistance of the MOS transistor, and improves the current driving power of the MOS transistor. By so doing, it becomes possible to reduce the gate width, and to reduce the area of the diffused layer forming the source and drain region. The reduction of the area of the diffused layer is accompanied by a decrease in the junction capacity, and the fine patterning contributes to the enhancement of the operating speed as viewed also from this point.
However, accompanying the reduction in the area of the diffusion layer forming the source and drain region, the aperture of the contact hole that connects the diffused layer and a metallic wiring is also necessarily reduced, and an aperture smaller than 1 .mu.m square has become to be required. A similar situation also exists as to other diffused layers (diffused layers used for the wiring, the resistor element, and the like) other than the diffused layer forming the source and drain region. In addition, the reduction in the opening area of the contact hole leads to an increase in the contact resistance between the diffused layer and the metallic wiring. In the diffused layer forming the source and drain region, the increase of the contact resistance becomes a factor in obstructing the improvement of the current driving power of the MOS transistor. In particular, the effect is dominant in a MOS transistor which adapts the sub-micron design rules. Under these circumstances, there has been disclosed a method for copying with the increase of the contact resistance in Japanese Patent Application Laid Open No. 2-312 (Jan. 5, 1990).
The result of application of the method disclosed in the above-mentioned publication to the formation of a MOS transistor is as in the following. Namely, a gate oxide film and a gate electrode are formed on the surface of a silicon substrate of one conductivity type, a first diffused layer of the opposite conductivity type self-aligned to the gate electrode is formed, and an interlayer insulating film is formed all over the surface. Next, the interlayer insulating film and the diffused layer of the opposite conductivity type are sequentially etched using a photoresist film as the mask to form a contact hole (referred to as a groove type contact hole hereinafter) that penetrates the first diffused layer. After removal of the photoresist film an organic solvent including impurities for diffusion of the opposite conductivity type is applied all over the surface, and by subjecting the system to a heat treatment, a second diffused layer of the opposite conductivity type is formed on the surface of the silicon substrate (including a part of the first diffused layer) that is exposed to the groove type contact hole. The second diffused layer is connected to the first diffused layer. After removal of the organic solvent, a metallic wiring is formed. According to the method, the reduction in the contact area between the metallic wiring and the diffused layer can be avoided even when the aperture of the groove type contact hole is reduced, so that the increase in the contact resistance between the diffused layer and the metallic wiring can be suppressed.
In the aforementioned publication, no description is found as to the element isolation region of the semiconductor device and the positional relationship between the element isolation region and the groove type contact hole. In the element isolation region of a semiconductor device that includes a MOS transistor, accompanying the fine patterning of the semiconductor device, combined use of a groove type element isolation region and a LOCOS type field oxide film is being adopted. In that case, a groove type element isolation region surrounding the periphery of the semiconductor device such as MOS transistor is formed. As to the positional relation (space between the two) between the element insulation region and the groove type contact hole, it is generally necessary to have a space between the element isolation region and the groove type contact hole which is greater than the value of the mask alignment margin of a photoresist film for the formation of the groove type contact hole. The reason for this is to avoid the etching of the element isolation region at the time of formation of the groove type contact hole.
The method in the above-mentioned publication will be considered for the case of an N-channel MOS transistor in which a LOCOS type field oxide film is adopted as the element isolation region as an example. In forming a semiconductor device consisting of an N-channel MOS transistor according to the quarter-micron design rules, first, a LOCOS type field oxide film with thickness of about 0.3 .mu.m and a gate oxide film with thickness of about 7-10 nm are formed on the surface of a silicon substrate with a P-type impurity concentration of (2 to 3).times.10.sup.17 cm.sup.-3. The smallest width of the field oxide film is 0.35 .mu.m. Next, a gate electrode with thickness of about 0.3 .mu.m and gate length of 0.25 .mu.m is formed. This gate electrode is formed of a polycrystalline silicon film or a polycide film. An N.sup.- -type diffused layer with junction depth of about 0.2 .mu.m is formed in self-alignment with the gate electrode. Next, a spacer with thickness of about 0.1 .mu.m consisting of a silicon oxide film is formed on the side faces of the gate electrode. An N.sup.+ -type diffused layer with junction depth of about 0.1 .mu.m is formed in self-alignment with the spacers. In this case, a first diffused layer is constituted of the N.sup.- -type diffused layer and the N.sup.+ -type diffused layer. Next, an interlayer insulating film consisting of a BPSG film with thickness of about 0.5 .mu.m is formed all over the surface. Then, a groove type contact hole with opening area of 0.4 .mu.m square which penetrates the N.sup.- -type diffused layer is formed by anisotropic etching by CF.sub.4 that uses a photoresist film as the mask. The mask alignment margin at this time is .+-.0.1 .mu.m. The height of the surface of the silicon substrate (N.sup.+ -type diffused layer) from the bottom face of the groove type contact hole is about 0.25 .mu.m. Next, an N.sup.+ -type diffused layer with junction depth of about 0.15 .mu.m which forms a second diffused layer is formed by means of the tilted rotation ion implantation method that uses arsenic or phosphorus on the surface of the silicon substrate (including a part of the N.sup.+ -type and N.sup.- -type diffused layers that form the first diffused layer). Next, an N.sup.+ -type polycrystalline silicon film or a tungsten film is embedded in the groove type contact hole, and a metallic wiring consisting of an aluminum alloy film is formed.
In this N-channel MOS transistor, there is required a space of about 0.4 .mu.m ("junction depth of the second diffused layer"+"increase in the depletion layer of the second diffused layer") between the gate electrode and the groove type contact hole because of the increase of about 0.25 .mu.m in the depletion layer of the second diffused layer to which is applied a power supply voltage. The reason for this is to prevent the fluctuation in the current driving power of the MOS transistor due to the presence of the second diffused layer. Similarly, when the width of the field oxide film is equal to the minimum allowable width, a space of about 0.4 .mu.m is required between the field oxide film and the groove type contact hole. The presence of this space is detrimental to the fine patterning of the semiconductor device. Moreover, the presence of this space brings about an increase in the junction capacitance of the diffused layer leading to an increase of the junction capacitance that exceeds the cancelation of the increase in the stray capacitance due to decrease in the contact resistance, which is an obstacle to the enhancement of the operating speed of the semiconductor device.
When the method disclosed in the aforementioned publication is applied to a semiconductor device that uses both of a groove type element isolation region and a LOCOS type field oxide film as an element isolation region, a groove type element isolation region is formed around the element isolation region, in the example of an N-channel MOS transistor. In this case, the space between the groove type contact hole and the gate electrode has the same value as in the above. When the height from the bottom face of the groove type element isolation region to the top face of the first diffused layer is smaller than the height from the bottom face of the second diffused layer to the top face of the first diffused layer, a space of about 0.4 .mu.m is required between the groove type contact hole and the groove type element isolation region, analogous to the case of the LOCOS type field oxide film described in the above. When the height from the bottom face of the groove type element isolation region to the top face of the first diffused layer is greater than the height from the bottom face of the second diffused layer to the top face of the first diffused layer, the space between the groove type contact hole and the groove type element isolation region requires a value (0.15 .mu.m, for example) greater than 0.1 .mu.m which is the mask alignment margin. Because of this, it becomes possible to give fine geometry to, and to prevent the increase in the junction capacitance of, the semiconductor device, but fine patterning beyond that is not feasible. The situation is analogous for the diffused layers other than the diffused layer forming the source and drain region.